The scaling of flash memory cells presents a number of challenges, one of which is to control the amount of floating gate endcap, that is, the amount by which the floating gate of a flash cell overhangs the active substrate of the cells into the isolation regions.
A conventional electrically erasable nonvolatile flash cell 100 is shown in FIG. 1 stacked with other similar cells at each side thereof, only half of each of the similar cells having been shown on each side of cell 100. Flash cell 100 includes polysilicon floating gate 102 formed on the tunnel dielectric 104 which is formed on the silicon region 106. An interpoly dielectric 108 is formed on the polysilicon floating gate, a control gate 110 is formed on the interpoly dielectric layer 108, and a pair of source/drain regions are formed along laterally opposite sidewalls of floating gate electrode 102. To store information in memory device 100, charge is stored on floating gate 102. To erase memory device 100, charge is removed from floating gate 102. A problem with memory storage cell 100 shown in FIG. 1, is that it has become difficult to further scale down its width and length to form smaller area cells and higher density memory circuits. In particular, scaling of the flash cell typically requires that a half pitch of the process node equal two times the floating gate endcap (FGEC), plus two times the interpoly dielectric thickness (IPD), plus the control gate width (CGW), as shown in FIG. 1. Conventionally, FGEC is typically about 10 nm, making the scaling of a 45 nm flash cell extremely challenging, and that of a 32 nm flash cell or lower almost impossible.
Current methods of solving the above problem involve either de-scaling the flash cell, that is, making the cell size larger than the half pitch of the process node described above, and/or by trading the line/space ratio to descale the isolation width, that is, the width of isolation regions such as regions 115 of memory device 100, to allow for material from the isolation region to be laterally etched during the removal of the original buffer oxide layer used as part of a formation of the isolation regions. In other words, the prior art makes the lines smaller, and the spaces much bigger. However, an optimum device performance would occur when the lines are at least equal in width to the spacer, if not wider. Thus, both of the above methods are undesirable to the extent that they trade flash cell performance for process limitations.
The prior art fails to provide a method of forming a flash cell that allows a reliable scaling of the flash cell into the 45 nm range and below.